Simulation-Based Analysis of a Hardware Mechanism to Support Isolation in Mixed-Criticality Network on Chip

Spatial and temporal isolation is a key issue in embedded systems running multiple tasks with different criticality levels (i.e. mixed-criticality embedded systems). This is particularly relevant for embedded systems based on multi core/processor (i.e. parallel) architectures. In such a context, this work focuses on Network on Chip (NoC) architectures and proposes a hardware mechanism designed to be introduced directly into network interfaces. Such a mechanism supports the isolation of multiple tasks with different criticality levels by controlling the exchange of messages while introducing very limited overhead on the monitored NoC. Then, the proposed mechanism is analyzed by means of two different simulations approaches for behavior validation, feasibility check, and scalability evaluation. The overall results show that the proposed mechanism is suitable to support mixed-criticality parallel embedded systems based on NoC architectures.